An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking

A new iterative multiplier based on a self-timed clocking scheme is presented. To reduce the area required for the multiplier, a small partial CSA array consisting of only two CSA rows is iteratively used to complete a multiplication. The partial CSA array is controlled by a fast internal clock generated using a self-timed technique. Compared with the array implementation, the proposed multiplier yields an 86.6% area reduction for 64×64 multiplication at the expense of 18.8% slow down. The 32×32 multiplier implemented in 0.35μm CMOS technology has a size of 0.495×0.215 mm, a latency of 19ns at 3.3V.